Address Translation Related Arm-v8a Features

On Arm-v8a, there are some kinds of extension related to address translation:

• FEAT_LPA : Extends (I)PA for 64KiB page size
• FEAT_VPA : Extends VA for 64KiB page size
• FEAT_LPA2: Extends (I)PA and VA for 4KiB and 16KiB page size

In this article I will introduce how they impact the translation of virtual addresses.

Generally, these features support longer address sizes. They extend the size of physical addresses (PA) or virtual addresses (VA) from 48 bits to 52 bits. They impact the address translation via the Translation Table Base Register (TTBRn_BLx) and Translation Table descriptor.

Large PA and IPA support

“Large PA and IPA support” (FEAT_LPA) is an optional feature in Armv8.2 implementations.

The feature FEAT_LPA extends PA and IPA space. It only affect 64KB pages. Specifically, the feature:

• Allows a larger intermediate physical address (IPA) and PA space of up to 52 bits when using the 64KB translation granule.
• Allows a level 1 block size where the block covers a 4TB address range for the 64KB translation granule if the implementation support 52 bits of PA.

To determine if the feature FEAT_LPA is present or not, software need to checkout PARange field of system register ID_AA64MMFR0_EL1. When ID_AA64MMFR0_EL1.PARange has value 0b0110, FEAT_LPA is enabled.

ID_AA64MMFR0_EL1

ID_AA64MMFR0_EL1, “AArch64 Memory Model Feature Register 0”, provides information about the implemented memory model and memory management support in AArch64 state.

PARange, bits [3:0]

This field indicates the Physical Address range that is supported. Defined values are:

• 0b0000 : 32 bits, 4GB.
• 0b0001 : 36 bits, 64GB.
• 0b0010 : 40 bits, 1TB.
• 0b0011 : 42 bits, 4TB.
• 0b0100 : 44 bits, 16TB.
• 0b0101 : 48 bits, 256TB.
• 0b0110 : 52 bits, 4PB (only available with feature FEAT_LPA).

Impact on address translation

Handling bits[51:48] of the PA or IPA:

• For a stage 1 translation, bits[5:2] of TTBR0_ELx or TTBR1_ELx holds bits[51:48] of the address of the translation table to be used for the initial lookup of that translation regime.
• For a stage 2 translation, bits[5:2] of VTTBR_EL2 or VSTTBR_EL2 holds bits[51:48] of the address of the translation table to be used for the initial lookup of the stage 2 translation.
• Bits[15:12] of each valid Translation Table descriptor hold bits[51:48] of the output address, or of the address of the translation table to be used for the lookup at the next level of translation.

Large VA support

“Large VA support” (FEAT_LVA) is another optional feature in Armv8.2 implementations. It supports a larger VA space for each translation table base register of up to 52 bits. Like FEAT_LPA, this feature only affects 64KB pages.

FEAT_LVA is indicated by VARange field of system register ID_AA64MMFR2_EL1.

ID_AA64MMFR2_EL1

ID_AA64MMFR2_EL1, “AArch64 Memory Model Feature Register 2”, provides information about the implemented memory model and memory management support in AArch64 state.

VARange, bits [19:16]
This field indicates support for a larger virtual address:

• 0b0000 : VMSAv8–64 supports 48-bit VAs.
• 0b0001 : VMSAv8–64 supports 52-bit VAs when using the 64KB translation granule.

Larger physical address for 4KB and 16KB translation granules

The 2 features previously mentioned extend VA and (I)PA respectively, but they are all limited to 64KB granule. For smaller granules, an optional feature called “Larger physical address for 4KB and 16KB translation granules” (FEAT_LPA2) was introduced in Armv8.7.

FEAT_LPA2 depends on FEAT_LPA and FEAT_LVA.

The feature extends VA, IPA and PA all up to 52 bits with 4KB or 16KB granule size. Specifically:

• Allows a larger VA space for each translation table base register of up to 52 bits when using the 4KB or 16KB translation granules.
• Allows a larger intermediate physical address (IPA) and PA space of up to 52 bits when using the 4KB or 16KB translation granules.
• Allows a level 0 block size where the block covers a 512GB address range for the 4KB translation granule if the implementation supports 52 bits of PA.
• Allows a level 1 block size where the block covers a 64GB address range for the 16KB translation granule if the implementation supports 52 bits of PA.

The feature FEAT_LPA2 is indicated by following fields of system register ID_AA64MMFR0_EL1:

• TGran4_2, bits [43:40]
  Indicates support for 4KB memory granule size at stage 2:
  - 0b0000 : Support for 4KB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field.
  - 0b0001 : 4KB granule not supported at stage 2.
  - 0b0010 : 4KB granule supported at stage 2.
  - 0b0011 : (For FEAT_LPA2 only) 4KB granule at stage 2 supports 52-bit input and output addresses.
• TGran16_2, bits [35:32]
  Indicates support for 16KB memory granule size at stage 2:
  - 0b0000 : Support for 16KB granule at stage 2 is identified in the
  ID_AA64MMFR0_EL1.TGran16 field.
  - 0b0001 : 16KB granule not supported at stage 2.
  - 0b0010 : 16KB granule supported at stage 2.
  - 0b0011 : (For FEAT_LPA2 only) 16KB granule at stage 2 supports 52-bit input and output addresses.
• TGran4, bits [31:28]
  Indicates support for 4KB memory translation granule size:
  - 0b0000 : 4KB granule supported.
  - 0b0001 : (For FEAT_LPA2 only) 4KB granule supports 52-bit input and output addresses.
  - 0b1111 : 4KB granule not supported.
• TGran16, bits [23:20]
  Indicates support for 16KB memory translation granule size:
  - 0b0000 : 16KB granule not supported.
  - 0b0001 : 16KB granule supported.
  - 0b0010 : (For FEAT_LPA2 only) 16KB granule supports 52-bit input and output addresses.

Impact on address translation

If FEAT_LPA2 is implemented, TCR_ELx.DS and VTCR_EL2.DS control when the 4KB and 16KB translation granules can use an address size greater than 48 bits:

• When DS==0, the maximum address size for the translation regime is 48 bits.
• When DS==1, the maximum address size for the translation regime is 52 bits.

If FEAT_LPA2 is implemented, and TCR_ELx.DS and VTCR_EL2.DS is 1. For a translation regime, the 52-bit IPA and PA size is supported in the 4KB and 16KB translation granules as follows:

• Bits[49:48] of each valid Translation Table descriptor hold bits[49:48] of the output address, or of the address of the translation table to be used for the initial lookup at the next level of translation.
• Bits[9:8] of each valid Translation Table descriptor hold bits[51:50] of the output address, or of the address of the translation table to be used for the initial lookup at the next level of translation.
• For a stage 1 translation, bits[5:2] of TTBR0_ELx or TTBR1_ELx holds bits[51:48] of the address of the translation table to be used for the initial lookup of that translation regime.
• For a stage 2 translation, bits[5:2] of VTTBR_EL2 or VSTTBR_EL2 holds bits[51:48] of the address of the translation table to be used for the initial lookup of the stage 2 translation.

Reference

• [1] Arm Architecture Reference Manual for A-profile architecture